8086 microprocessor was designed by Intel between early 1976 and mid-1978.
It is a 16 bit microprocessor (has 16 data lines) and 20 address lines. It is
designed in such a manner that it can provide upto 1 MB storage. This is an
enhanced version of 8085 microprocessor so it consists of powerful instruction
set which provides tasks like multiplication and division easily.
8086 has 2 modes-
mode: This mode is suitable for system having multi processors.
mode: This mode is suitable for system having single processor.
As mentioned above that 8086 is an enhanced version
of 8085 so here are some of the differences listed below
bit address bus
bit address bus
access upto 1MB
access upto 64Kb
supports pipelined structure
address 2^16=65536 devices
address 2^8=256 devices
Features of 8086:
It has instruction queue which is
capable of storing 6 instruction bytes from the memory resulting in faster
It is a 16 bit processor having 16 bit
ALU, 16 bit registers, 16 bit external data bus and internal data bus resulting
in faster processing.
It uses two stages of pipelining first
is fetch and second is execute which enhances or improves the performance.
Fetch stage can pre-fetch upto 6 bytes
of instructions and stores in queue.
Execute stage executes instructions.
It consists of 29000 transistors and has
256 vectored interrupts.
It is available in three versions based
8086 – 5MHz
8086 – 8MHz
8086 – 10MHz
Architecture of 8086:
The architecture comprises of two segments:-
BIU (Bus Interface Unit): It generates the 20 bit physical address for
memory access and fetches instruction from memory. It then transfers data to
and from the memory and Input and Output devices. It supports pipelining using
the 6 byte instruction queue.
The main components
of the BIU are as follows:
Code Segment register: It holds the base
address for the CS and all programs are stored in this segment.
Data Segment register: It holds the base
address for DS.
Stack Segment register: It holds the base
address for the SS.
Extra Segment register: It holds the base
address for the ES.
Instruction Pointer: It is a 16 bit register. It
holds offset of the next instructions in the CS then address of the next
instruction is calculated as CS x 10H + IP after that IP is incremented
after every instruction byte is fetched and at last IP gets a new value
whenever a branch occurs.
Instruction stream byte queue:
execution unit (EU) is supposed to decode or execute an instruction.
does not require the use of buses.
EU is busy in decoding and executing an instruction, the BIU fetches up to
six instruction bytes for the next instructions.
bytes are called as the pre-fetched bytes and they are stored in a first
in first out (FIFO) register set, which is called as a queue.